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| TDA9109A LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR FEATURES General s SYNC PROCESSOR s 12V SUPPLY VOLTAGE s 8V REFERENCE VOLTAGE s HORIZONTAL LOCK/UNLOCK OUTPUT 2 s READ/WRITE I C INTERFACE s VERTICAL MOIRE s B+ REGULATOR - Internal PWM generator for B+ current mode step-up converter - Switchable to step-down converter - I2C adjustable B+ reference voltage - Output Pulses Synchronized on Horizontal Frequency - Internal Maximum Current Limitation Horizontal s Self-adaptative s Dual PLL concept s 150kHz maximum frequency s X-ray protection input 2 s I C controls: Horizontal duty-cycle, H-position Vertical s Vertical ramp generator s 50 to 185Hz AGC loop s Geometry tracking with Vpos & Vamp 2 s I C controls: Vamp, Vpos, S-corr, C-corr s DC breathing compensation I2C Geometry corrections s Vertical parabola generator (Pin Cushion - E/W, Keystone, Corner Correction) s Horizontal dynamic phase (Side Pin Balance & Parallelogram) s Horizontal and vertical dynamic focus (Horizontal focus amplitude, Horizontal focus symmetry, Vertical focus amplitude) Version 4.2 June 2000 1/47 DESCRIPTION The TDA9109A is a monolithic integrated circuit assembled in a 32-pin shrink dual in line plastic package. This IC controls all the functions related to the horizontal and vertical deflection in multimode or multi-frequency computer display monitors. The internal sync processor, combined with the very powerful geometry correction block, make the TDA9109A suitable for very high performance monitors, using very few external components. The horizontal jitter level is very low. It is particularly well-suited to high-end 15" and 17" monitors. Combined with the ST7275 Microcontroller family, TDA9206 (Video preamplifier) and STV942x (OnScreen Display controller), the TDA9109A allows fully I2C bus-controlled computer display monitors to be built with a reduced number of external components . SHRINK32 (Plastic Package) ORDER CODE: TDA9109A 1 TABLE OF CONTENTS PIN CONNECTIONS PIN CONNECTIONS QUICK REFERENCE DATA BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL DATA I2C READ/WRITE SYNC PROCESSOR HORIZONTAL SECTION VERTICAL SECTION DYNAMIC FOCUS SECTION GEOMETRY CONTROL SECTION B+ SECTION TYPICAL OUTPUT WAVEFORMS I2C BUS ADDRESS TABLE I2C BUS ADDRESS TABLE OPERATING DESCRIPTION 4 5 6 8 9 9 10 10 11 13 15 16 18 20 24 25 27 1 GENERAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.1Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.2I2C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.3Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.4Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5Sync Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6Sync Identification Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.7IC status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.8Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.9Sync Processor Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2 HORIZONTAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.1Internal Input Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5X-RAY Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.6Horizontal and Vertical Dynamic Focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3 VERTICAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2I2C Control Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3Vertical Moire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4Basic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5E/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . . . 36 . 3.6Dynamic Horizontal Phase Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2/47 2 TABLE OF CONTENTS 4 DC/DC CONVERTER PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.1Step-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2Step-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3Step-up and Step-down Mode Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INTERNAL SCHEMATICS 39 PACKAGE MECHANICAL DATA 46 3 3/47 TDA9109A PIN CONNECTIONS H/HVIN VSYNCIN HLOCKOUT PLL2C C0 R0 PLL1F HPOSITION HFOCUSCAP FOCUS-OUT HGND HFLY HREF COMP REGIN ISENSE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 5V SDA SCL VCC BOUT GND HOUT XRAY EWOUT VOUT VCAP VREF VAGCCAP VGND BREATH B+GND 4/47 TDA9109A PIN CONNECTIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name H/HVIN VSYNCIN HLOCKOUT PLL2C C0 R0 PLL1F HPOSITION HFOCUSCAP FOCUS OUT HGND HFLY HREF COMP REGIN ISENSE B+GND BREATH VGND VAGCCAP VREF VCAP VOUT EWOUT XRAY HOUT GND BOUT VCC SCL SDA 5V Function TTL compatible Horizontal sync Input (separate or composite) TTL compatible Vertical sync Input (for separated H&V) First PLL Lock/Unlock Output (0 V: Unlocked - 5 V: Locked) Second PLL Loop Filter Horizontal Oscillator Capacitor Horizontal Oscillator Resistor First PLL Loop Filter Horizontal Position Filter (capacitor to be connected to HGND) Horizontal Dynamic Focus Oscillator Capacitor Mixed Horizontal and Vertical Dynamic Focus Output Horizontal Section Ground Horizontal Flyback Input (positive polarity) Horizontal Section Reference Voltage (to be filtered) B+ Error Amplifier Output for frequency compensation and gain setting Regulation Input of B+ control loop Sensing of external B+ switching transistor current,or switch for step-down converter Ground (related to B+ reference adjustment) DC Breathing Input Control (compensation of vertical amplitude against EHV variation) Vertical Section Ground Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator Vertical Section Reference Voltage (to be filtered) Vertical Sawtooth Generator Capacitor Vertical Ramp Output (with frequency independant amplitude and S or C Corrections if any). It is mixed with vertical position voltage and vertical moire. Pin Cushion - E/W Correction Parabola Output X-RAY protection input (with internal latch function) Horizontal Drive Output (NPN open collector) General Ground (referenced to V CC) B+ PWM Regulator Output Supply Voltage(12V typ) I2C Clock Input I2C Data Input Supply Voltage (5V typ.) 5/47 TDA9109A QUICK REFERENCE DATA Parameter Horizontal Frequency Autosynch Frequency (for given R0 and C0. Can be easily increased by application) Horizontal Sync Polarity Input Polarity Detection (on both Horizontal and Vertical Sections) TTL Composite Sync Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section) I C Control for H-Position XRAY Protection I C Horizontal Duty Cycle Adjustment I2C Free Running Frequency Adjustment 2 2 Value 15 to 150 1 to 4.5 f0 YES YES YES YES 10 YES 30 to 65 NO YES NO YES NO NO 35 to 200 50 to 185 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES Unit kHz % % Stand-by Function Dual Polarity H-Drive Outputs Supply Voltage Monitoring PLL1 Inhibition Possibility Blanking Outputs Vertical Frequency Vertical Autosync (for 150nF on Pin 22 and 470nF on Pin 20) Vertical S-Correction (optimized for super flat tube) Vertical C-Correction Vertical Amplitude Adjustment DC Breathing Control on Vertical Amplitude Vertical Position Adjustment East/West (E/W) Parabola Output (also known as Pin Cushion Output) E/W Correction Amplitude Adjustment Keystone Adjustment Corner Correction with Amplitude Adjustment Internal Dynamic Horizontal Phase Control Side Pin Balance Amplitude Adjustment Parallelogram Adjustment Tracking of Geometric Corrections with Vertical Amplitude and Position Reference Voltage (both on Horizontal and Vertical) Dynamic Focus (both Horizontal and Vertical) I C Horizontal Dynamic Focus Amplitude Adjustment I2C 2 2 Hz Hz Horizontal Dynamic Focus Symmetry Adjustment I C Vertical Dynamic Focus Amplitude Adjustment 6/47 TDA9109A Parameter Detection of Input Sync (biased from 5V alone) Vertical Moire Controlled V-Moire Amplitude Frequency Generator for Burn-in Fast I C Read/Write B+ Regulation adjustable by I C Horizontal Size Control 2 2 Value YES YES YES NO 400 YES NO Unit kHz 7/47 8/47 BLOCK DIAGRAM TDA9109A PLL1F 7 POSITION 8 R0 C0 6 5 HFLY 12 PLL2C 4 Phase Shifter H-Duty (7bits) HOUT 26 Hout Buffer Safety Processor 11 HGND 19 VGND 17 BGND 29 VCC 25 XRAY 28 BOUT 16 ISENSE 14 COMP 15 REGIN + Phase/Frequency Comparator H-Phase(7bits) H/HVIN 1 VSYNCIN 2 Sync Input Select (1bit) Sync Processor VCO Phase Comparator Lock/Unlock Identification SPin bal 7bits x2 B+ Controller x HLOCKOUT 3 Paral 7bits VDFAMP 7bits x2 5V Internal reference (7bits) 10 FOCUS Geometry Tracking SDA 31 SCL 30 GND 27 5V 32 E/Wpcc 7bits Keyst. 7 bits Corner 7bits x4 x2 Amp 2 Symmetryx 2x7bits 7 bits I2C Interface 7 bits Vertical Oscillator Ramp Generator VPOS 7bits VAMP 7bits 9 HFOCUSCAP 24 EWOUT S and C Correction Href Vref x HREF 13 VREF 21 VerticalMoire Cancel 7bits+ON/OFF VSYNC TDA9109A 22 20 18 23 VCAP VAGCCAP BREATH VOUT TDA9109A ABSOLUTE MAXIMUM RATINGS Symbol VCC VDD Supply Voltage (Pin 29) Supply Voltage (Pin 32) Max Voltage on V IN Pin 4 Pin 9 Pin 5 Pins 6, 7, 8, 14, 15, 16, 20, 22 Pins 10, 18, 23, 24, 25, 26, 28 Pins 1, 2, 3, 30, 31 Human Body Model, 100pF Discharge 1.5k EIAJ Norm, 200pF Discharge through 0 Parameter Value 13.5 5.7 4.0 5.5 6.4 8.0 VCC VDD 2 300 -40, +150 +150 0, +70 Unit V V V V V V V V kV V C C C VESD Tstg Tj Toper ESD susceptibility through Storage Temperature Junction Temperature Operating Temperature THERMAL DATA Symbol R th(j-a) Parameter Max. Junction-Ambient Thermal Resistance Value 65 Unit C/W 9/47 TDA9109A I2C READ/WRITE Electrical Characteristics (VDD = 5V, Tamb = 25C) Symbol I C PROCESSOR (See ) Fscl Tlow Thigh Vinth VACK I 2C leak Note: 1 Maximum Clock Frequency Low period of the SCL Clock High period of the SCL Clock SDA and SCL Input Threshold Acknowledge Output Voltage on SDA input with 3mA Leakage current into SDA and SCL with no logic supply Pin 30 Pin 30 Pin 30 Pins 30, 31 Pin 31 VDD = 0 Pins 30, 31 = 5 V 1.3 0.6 2.2 0.4 20 400 kHz s s V V A 2 1 Parameter Test Conditions Min. Typ. Max. Units See also I2 C Bus Address Table. SYNC PROCESSOR Operating Conditions (VDD = 5V, Tamb = 25C) Symbol HsVR MinD Mduty VsVR VSW VSmD VextM Parameter Voltage on H/HVIN Input Minimum Horizontal Input Pulses Duration Maximum Horizontal Input Signal Duty Cycle Voltage on VSYNCIN Minimum Vertical Sync Pulse Width Maximum Vertical Sync Input Duty Cycle Maximum Vertical Sync Width on TTL H/Vcomposite Test Conditions Pin 1 Pin 1 Pin 1 Pin 2 Pin 2 Pin 2 Pin 1 0 5 15 750 Min. 0 0.7 25 5 Typ. Max. 5 Units V s % V s % s Electrical Characteristics (VDD = 5V, Tamb = 25C) Symbol VINTH RIN VoutT Note: 2 Parameter Horizontal and Vertical Input Logic Level (Pins 1, 2) Horizontal and Vertical Pull-Up Resistor Extracted Vsync Integration Time (% of TH) on H/V Composite (see 2) T H is the Horizontal period. Test Conditions High Level Low Level Pins 1, 2 C0 = 820pF 26 Min. 2.2 0.8 250 35 Typ. Max. Units V V k % 10/47 TDA9109A HORIZONTAL SECTION Operating Conditions Symbol VCO I0max F(max.) I12m HOI Max Current from Pin 6 Maximum Oscillator Frequency Maximum Input Peak Current Horizontal Drive Output Maximum Current Pin 12 Pin 26, Sunk current Pin 6 1.5 150 5 30 mA kHz mA mA Parameter Test Conditions Min. Typ. Max. Units OUTPUT SECTION Electrical Characteristics (VDD = 12V, Tamb = 25C)) Symbol VCC VDD ICC IDD V REF-H VREF-V IREF-H IREF-V Parameter Supply Voltage Supply Voltage Supply Current Supply Current Horizontal Reference Voltage Vertical Reference Voltage Max. Sourced Current on VREF-H Test Conditions Pin 29 Pin 32 Pin 29 Pin 32 Pin 13, I = -2mA Pin 21, I = -2mA Pin 13 Pin 21 7.6 7.6 Min. 10.8 4.5 Typ. 12 5 50 5 8.2 8.2 8.8 8.8 5 5 Max. 13.2 5.5 Units V V mA mA V V mA mA SUPPLY AND REFERENCE VOLTAGES Max. Sourced Current on VREF-V 1st PLL SECTION HpoIT Delay Time for detecting polarity change (see 3) VCO Control Voltage (Pin 7) Pin 1 V REF-H = 8.2V fH(Max.) R 0 = 6.49k, C 0 =820pF % of Horizontal Period Sub-Address 01 Byte x1111111 Byte x1000000 Byte x0000000 PLL1 is Unlocked PLL1 is Locked R 0 = 6.49k, C 0 = 820pF fo 0.75 ms Vvco 1.4 6.4 15.9 10 V V kHz/V % Vcog Hph VCO Gain (Pin 7) Horizontal Phase Adjustment (see 4) Horizontal Phase Setting Value (Pin 8) (see 4) Minimum Value Typical Value Maximum Value PLL1 Filter Current Charge Free Running Frequency Free Running Frequency Thermal Drift (No drift on external components) (see 5) PLL1 Capture Range DC level pin 3 when PLL1 is locked Vbmi Vbtyp Vbmax IPII1U IPII1L fo dfo/dT 2.9 3.5 4.2 140 1 22.8 V V V A mA kHz ppm/ C kHz kHz V -150 fH(Min.) fH(Max.) (See Note 6) fo+0.5 4.5fo 5 CR HUnlock 11/47 TDA9109A Symbol Parameter Flyback Input Threshold Voltage (Pin 12) Horizontal Jitter (See ) Horizontal Drive Output Duty-Cycle (Pin 26) (see 8) X-RAY Protection Input Threshold Voltage, Internal Clamping Levels on 2nd PLL Loop Filter (Pin 4) Threshold Voltage to Stop H-Out, VOut, B-Out and Reset XRAY when VCC < VSCinh (see Figure14) Horizontal Drive Output (low level) 7 Test Conditions Min. Typ. Max. Units 2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION FBth Hjit HDmin HDmax XRAYth Vphi2 0.65 At 31.4kHz Sub-Address 00 Byte x1111111 Byte x0000000 (see 9) Pin 25, see Figure 14 Low Level High Level Pin 29 Pin 26, IOUT = 30mA 7.6 0.75 70 30 65 8.2 1.6 4.2 7.5 0.4 8.8 V ppm % % V V V V V VSCinh HDvd Note: 3 Note: 4 Note: 5 Note: 6 Note: 7 Note: 8 Note: 9 This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync. See Figure 10 for explanation of reference phase. These parameters are not tested on each unit. They are measured during our internal qualification. A larger range may be obtained by application. Hjit = 106 x (Standard deviation/Horizontal period) Duty Cycle is the ratio between the output transistor OFF time and the period. The power transistor is controlled OFF when the output transistor is OFF. Initial Condition for Safe Operation Start Up. 12/47 TDA9109A VERTICAL SECTION Operating Conditions Symbol OUTPUTS SECTION R LOAD Minimum Load for less than 1% Vertical Amplitude Drift Pin 20 65 M Parameter Test Conditions Min. Typ. Max. Units Electrical Characteristics (VCC = 12V, Tamb = 25C) Symbol VRB VRT VRTF VSTD VFRF ASFR RAFD Rlin Parameter Voltage at Ramp Bottom Point Voltage at Ramp Top Point (with Sync) Voltage at Ramp Top Point (without Sync) Vertical Sawtooth Discharge Time Vertical Free Running Frequency (See 11) AUTO-SYNC Frequency (See 12) Ramp Amplitude Drift Versus Frequency at Maximum Vertical Amplitude (see 10) Ramp Linearity on Pin 22 (See 11) Vertical Position Adjustment Voltage (Pin 23 - VOUT mean value) Test Conditions Pin 22 Pin 22 Pin 22 Pin 22, C22 = 150nF C 22 = 150nF C 22 = 150nF 5% C 22 = 150nF 50Hz< f < 185Hz 2.5V < V27 < 4.5V Sub Address 06 Byte 00000000 Byte 01000000 Byte 01111111 Sub Address 05 Byte 10000000 Byte 11000000 Byte 11111111 50 200 0.5 3.2 3.6 4.0 2.15 3.0 3.9 5 Sub Address 07 Byte 11111111 V/VPP at TV/4 V/VPP at 3TV/4 Sub Address 08 V/VPP at TV/2 Byte 10000000 Byte 11000000 Byte 11111111 Sub Address 0C Byte 01X11111 Min. Typ. 2.1 5.1 VRT0.1 70 100 185 Max. Units V V V s Hz Hz ppm/ Hz % V V V V V V mA VERTICAL RAMP SECTION VPOS VOR Vertical Output Voltage (peak-to-peak on Pin 23) Vertical Output Maximum Current (Pin 23) Max Vertical S-Correction Amplitude (See 13) 0xxxxxxx inhibits S-CORR 11111111 gives max S-CORR VOI dVS -3.5 3.5 % % Ccorr Vertical C-Corr Amplitude 0xxxxxxx inhibits C-CORR -3 0 3 6 % % % mV VMOIRE Vertical Moire 13/47 TDA9109A Symbol Parameter DC Breathing Voltage Range (See 14) Vertical Output Variation versus DC Breathing Control (Pin 23) Test Conditions Min. Typ. Max. Units BREATHING COMPENSATION BRRANG BRADj V18 V18 > VREF-V 1V 14/47 TDA9109A DYNAMIC FOCUS SECTION Electrical Characteristics (VCC = 12V, Tamb = 25C) Symbol Parameter Test Conditions Pin 9, capacitor on HFOCUSCAP and C0 = 820pF, TH = 20s Start by HDFstart Independent of frequency R LOAD = 10k, Pin 10 Min. Typ. Max. Units HORIZONTAL DYNAMIC FOCUS FUNCTION Horizontal Dynamic Focus Sawtooth Minimum Level Maximum Level Horizontal Dynamic Focus Sawtooth Discharge Width Internal Fixed Phase Advance versus HFLY middle Bottom DC Output Level DC Output Voltage Thermal Drift (see 15) Horizontal Dynamic Focus Amplitude Min Byte xxx11111 Typ Byte xxx10000 Max Byte xxx00000 Horizontal Dynamic Focus Position Advance for Byte xxx11111 Delay for Byte xxx00000 Vertical Dynamic Focus Parabola (added to horizontal) Amplitude with VAMP and VPOS Typical Min. Byte xx000000 Typ. Byte xx100000 Max. Byte xx111111 Parabola Amplitude Function of VAMP (tracking between VAMP and VDF) with VPOS Typ. (see Figure 1 and 16) Parabola Asymmetry Function of VPOS Control (tracking between VPOS and VDF) with VAMP Max. A/B Ratio B/A Ratio Sub-Address 03, Pin 10, fH = 50kHz, Symmetric Wave Form Sub-address 04 For time reference see Figure 15 Sub-Address 0F 0 0.5 1 Sub-Address 05 Byte x0000000 Byte x1000000 Byte x1111111 Sub-Address 06 VPP VPP VPP VPP VPP VPP HDFst 2.2 4.9 400 1 2.1 200 V V ns s V ppm/ C VPP VPP VPP % % HDFdis HDFstart HDFDC TDFHD HDFamp 1 1.5 3.5 16 16 HDFKeyst VERTICAL DYNAMIC FOCUS FUNCTION (positive parabola) AMPVDF VDFAMP 0.6 1 1.5 VHDFKeyt Byte x0000000 Byte x1111111 0.52 0.52 Note: 15 These parameters are not tested on each unit. They are measured during our internal qualification. Note: 16 S and C correction are inhibited so the vertical output sawtooth has a linear shape. 15/47 TDA9109A GEOMETRY CONTROL SECTION Electrical Characteristics (VCC = 12V, Tamb = 25C) Symbol East/West E/W FUNCTION EW DC TDEWDC DC Output Voltage with: - typical VPOS - Keystone inhibited DC Output Voltage Thermal Drift Parabola Amplitude with: - Max. VAMP, - Typ. VPOS, - Keystone and Corner inhibited Parabola Amplitude Function of VAMP Control (tracking between VAMP and E/W) with: - Typ. VPOS, - Typ. E/W Amplitude, - Corner and Keystone inhibited (17) Keystone Adjustment Capability with: - Typ. VPOS, - E/W inhibited, - Corner inhibited and - Max. Vertical Amplitude (see 17 and Figure 4) Corner Adjustment Capability with: - Typ. VPOS, - E/W inhibited, - Keystone inhibited - Max. Vertical Amplitude Intrinsic Keystone Function of VPOS Control (tracking between VPOS and E/W) with: - Max. E/W Amplitude - Max. Vertical Amplitude A/B Ratio B/A Ratio Pin 24, see Figure 2 See 15 Subaddress 0A Byte 11111111 Byte 11000000 Byte 10000000 Subaddress 05 2.5 V ppm/ C VPP VPP VPP Parameter Test Conditions Min. Typ. Max. Units 100 EWpara 2.5 1.25 0 EWtrack Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 09 0.45 0.80 1.45 VPP VPP VPP KeyAdj Byte 10000000 Byte 11111111 Subaddress 10 Byte 11111111 Byte 11000000 Byte 10000000 Subaddress 06 1 1 VPP VPP EW Corner +3 0 -3 VPP VPP VPP KeyTrack Byte 00000000 Byte 01111111 0.52 0.52 16/47 TDA9109A Symbol Parameter Side Pin Balance Parabola Amplitude (Figure 3) with: - Max. VAMP, - Typ. VPOS - Parallelogram inhibited (see 17 & 19) Side Pin Balance Parabola Amplitude function of VAMP Control (tracking between VAMP and SPB) with - Max. SPB, - Typ. VPOS - Parallelogram inhibited (see 17 & 19) Parallelogram Adjustment Capability with: - Max. VAMP, - Typ. VPOS - Max. SPB (see 17 & 19) Intrinsic Parallelogram Function of VPOS Control (tracking between VPOS and DHPC) with: - Max. VAMP, - Max. SPB - Parallelogram inhibited (see 17 & 19) A/B Ratio B/A Ratio Test Conditions Subaddress 0D Min. Typ. Max. Units INTERNAL DYNAMIC HORIZONTAL PHASE CONTROL SPBpara Byte 11111111 Byte 10000000 Subaddress 05 +2.8 -2.8 %TH %TH SPBtrack Byte 10000000 Byte 11000000 Byte 11111111 Subaddress 0E 1 1.8 2.8 %TH %TH %TH ParAdj Byte 11111111 Byte 11000000 Subaddress 06 +2.8 -2.8 %TH %TH Partrack Byte x0000000 Byte x1111111 0.52 0.52 Note: 17 With Register 07 at Byte 0xxxxxxx (S correction is inhibited) and Register 08 at Byte 0xxxxxxx (C correction is inhibited), the vertical sawtooth has a linear shape. Note: 18 T H is the horizontal period. Note: 19 When not used, the DC breathing control pin must be connected to 12V. 17/47 TDA9109A B+ SECTION Operating Conditions Symbol FeedRes Parameter Minimum Feedback Resistor Test Conditions Resistor between Pins 15 and 14 Min. 5 Typ. Max. Units k Electrical Characteristics (VCC = 12V, Tamb = 25C) Symbol OLG UGBW IRI Parameter Error Amplifier Open Loop Gain Unity Gain Bandwidth Regulation Input Bias Current Test Conditions At low frequency ( 15) (see 15 Min. Typ. 85 6 0.2 1.4 Max. Units dB MHz A mA mA ) Current sourced by Pin 15 (PNP base) Current sourced by Pin 14 Current sunk by Pin 14 (See 20) Pin 16 Pin 16 Current sunk by Pin 16 (PNP base) % of horizontal period fo = 27kHz (See 21) V 28 with I28 = 10mA On error amp (+) input for Subaddress OB Byte 1000000 Byte 01111111 Byte 00000000 Pin 16 Pin 28 EAOI Error Amplifier Output Current 2 3 1.3 1 100 0.25 5 +20 -20 6 100 CSG MCEth ISI Tonmax B+OSV IVREF V REFADJ PWMSEL tFB+ Current Sense Input Voltage Gain Max Current Sense Input Threshold Voltage Current Sense Input Bias Current Maximum ON Time of the external power transistor B+Output Saturation Voltage Internal Reference Voltage Internal Reference Voltage Adjustment Range Threshold for step-up/step-down selection Fall Time V A % V V % % V ns Note: 20 0.5mA are sunk when B+ section is disabled. the purpose is to discharge the soft-start capacitor. Note: 21 The external power transistor is OFF during 400ns of the HFOCUSCAP discharge 18/47 TDA9109A Figure 1. Vertical Dynamic Focus Function Figure 2. E/W Output Figure 3. Dynamic Horizontal Phase Control Output Figure 4. Keystone Effect on E/W Output (PCC Inhibited) 19/47 TDA9109A TYPICAL OUTPUT WAVEFORMS Function Sub Address Pin Byte Specification Effect on Screen 10000000 Vertical Size 05 23 11111111 VOUTDC = 3.2V 00000000 Vertical Position DC Control VOUTDC = 3.6V 06 23 01000000 V OUTDC = 4.0V 01111111 0xxxxxxx: Inhibited Vertical S Linearity 07 23 11111111 = 20/47 TDA9109A Function Sub Address Pin Byte Specification Effect on Screen 0xxxxxxx : Inhibited Vertical C Linearity 08 23 10000000 = -3% 11111111 = +3% Horizontal Dynamic Focus with: Amplitude 03 10 X000 0000 -- X111 1111 -- Horizontal Dynamic Focus with: Symmetry 04 10 X000 0000 -- X111 1111 -- 21/47 TDA9109A Function Sub Address Pin Byte (E/W + Corner Inhibited) Specification Effect on Screen Keystone (Trapezoid) Control 10000000 09 24 0.4V EWDC 11111111 0.4V EWDC (Keystone + Corner Inhibited) E/W (Pin Cushion) Control 0A 24 10000000 EWDC 0V 11111111 EW DC 1.4V (Keystone+E/W Inhibited) 11111111 Corner Control 10 24 1.25V EW DC EW DC 10000000 1.25V (SPB Inhibited) Internal 2.8% T H Parallelogram Control 10000000 0E 11111111 2.8% T H 22/47 TDA9109A Function Sub Address Pin Byte Specification (Parallelogram Inhibited) Effect on Screen Internal Side Pin Balance Control 10000000 2.8% TH 0D 11111111 2.8% TH Vertical Dynamic Focus with Horizontal 0F 10 X111 1111 --X000 0000 --- 23/47 TDA9109A I2C BUS ADDRESS TABLE Slave Address (8C): Write Mode Sub Address Definition D8 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D3 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 D2 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Sync. Priority/Horizontal Focus Amplitude Refresh/Horizontal Focus Keystone Vertical Ramp Amplitude Vertical Position Adjustment S Correction C Correction E/W Keystone E/W Amplitude B+ Reference Adjustment Vertical Moire Side Pin Balance Parallelogram Vertical Dynamic Focus Amplitude E/W Corner Horizontal Drive Selection/Horizontal Duty Cycle X-ray Reset/Horizontal Position Slave Address (8D): Read Mode No sub address needed. 24/47 TDA9109A I2C BUS ADDRESS TABLE D8 WRITE MODE 00 Xray 1, reset [0] [HDrive 0, off [1], on0] Horizontal Duty Cycle [0] [0] [0] [0] [0] [0] D7 D6 D5 D4 D3 D2 D1 Horizontal Phase Adjustment [1] [0] [0] [0] [0] [0] [0] 01 02 03 Sync 0, Comp [1], Sep Detect Refresh [0], off Vramp 0, off [1], on Horizontal Focus Amplitude [1] [0] [0] [0] [0] Horizontal Focus Time Position [1] [0] [0] [0] [0] 04 Vertical Ramp Amplitude Adjustment [1] [0] [0] [0] [0] [0] [0] 05 Vertical Position Adjustment 06 S Select 1, on [0] C Select 1, on [0] E/W Key 0, off [1] E/W Sel 0, off [1] Test H 1, on [0], off Test V 1, on [0], off SPB Sel 0, off [1] Parallelo 0, off [1] [1] [0] [0] [0] [0] [0] [0] S Correction [1] [0] [0] [0] [0] [0] 07 C Correction [1] [0] [0] [0] [0] [0] 08 E/W Keystone [1] [0] [0] E/W Amplitude [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] 09 0A B + Reference Adjustment [1] Moire 1, on [0] [0] [0] [0] [0] Vertical Moire [0] [0] [0] [0] [0] [0] [0] 0B 0C Side Pin Balance [1] [0] [0] [0] [0] [0] 0D Parallelogram [1] [0] [0] [0] [0] [0] 0E 25/47 TDA9109A D8 0F Eq. Pulse 1, on [0], off Corner 1, on [0], off D7 D6 D5 D4 D3 D2 D1 Vertical Dynamic Focus Amplitude [1] [0] [0] [0] [0] [0] Corner Amplitude Adjustment [1] [0] [0] [0] [0] [0] 10 READ MODE Hlock 0, on [1], no Polarity Detection Vlock 0, on [1], no Xray 1, on [0], off H/V pol [1], negative V pol [1], negative Vext det [0], no det Sync Detection H/V det [0], no det V det [0], no det [x] Initial value Data is transferred with vertical sawtooth retrace. We recommend setting the unspecified bit to [0] in order to ensure compatibility with future devices. 26/47 TDA9109A OPERATING DESCRIPTION 1 GENERAL CONSIDERATIONS 1.1 Power Supply The typical values of the power supply voltages VCC and VDD are 12 V and 5 V respectively. Optimum operation is obtained for VCC between 10.8 and 13.2 V and VDD between 4.5 and 5.5 V. In order to avoid erratic operation of the circuit during the transient phase of VCC switching on, or off, the value of V CC is monitored: if VCC is less than 7.5 V typ., the outputs of the circuit are inhibited. Similarly, before VDD reaches 4 V, all the I2 C register are reset to their default value (see I 2C Control Table). In order to have very good power supply rejection, the circuit is internally supplied by several voltage references (typ. value: 8.2 V). Two of these voltage references are externally accessible, one for the vertical and one for the horizontal part. They can be used to bias external circuitry (if ILOAD is less than 5 mA). It is necessary to filter the voltage references by external capacitors connected to ground, in order to minimize the noise and consequently the "jitter" on vertical and horizontal output signals. 1.2 I2 C Control TDA9109A belongs to the I2C controlled device family. Instead of being controlled by DC voltages on dedicated control pins, each adjustment can be done via the I2C Interface. The I2C bus is a serial bus with a clock and a data input. The general function and the bus protocol are specified in the Philips-bus data sheets. The interface (Data and Clock) is a comparator whose threshold is 2.2 V with a 5 V supply. Spikes of up to 50 ns are filtered by an integrator and the maximum clock speed is limited to 400 kHz. The data line (SDA) can be used bidirectionally. In read-mode the IC sends reply information (1 byte) to the micro-processor. The bus protocol prescribes a full-byte transmission in all cases. The first byte after the start condition is used to transmit the IC-address (hexa 8C for write, 8D for read). 1.3 Write Mode In write mode the second byte sent contains the subaddress of the selected function to adjust (or controls to affect) and the third byte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the third byte no stop or start condition is detected, the circuit increments automatically by one the momentary subaddress in the subaddress counter (auto-increment mode). So it is possible to transmit immediately the following data bytes without sending the IC address or subaddress. This can be useful to reinitialize all the controls very quickly (flash manner). This procedure can be finished by a stop condition. The circuit has 18 adjustment capabilities: 3 for the horizontal part, 4 for the vertical, 3 for the E/W correction, 2 for the dynamic horizontal phase control, 2 for the vertical and horizontal Moire options, 3 for the horizontal and the vertical dynamic focus and 1 for the B+ reference adjustment. 18 bits are also dedicated to several controls (ON/ OFF, Horizontal Forced Frequency, Sync Priority, Detection Refresh and XRAY reset). 1.4 Read Mode During the read mode the second byte transmits the reply information. The reply byte contains the horizontal and vertical lock/unlock status, the XRAY activation status and, the horizontal and vertical polarity detection. It also contains the sync detection status which is used by the MCU to assign the sync priority. A stop condition always stops all the activities of the bus decoder and switches to high impedance both the data and clock line (SDA and SCL). See I2C subaddress and control tables. 1.5 Sync Processor The internal sync processor allows the TDA9109A to accept: * * separated horizontal & vertical TTLcompatible sync signal composite horizontal & vertical TTLcompatible sync signal 27/47 TDA9109A 1.6 Sync Identification Status The MCU can read (address read mode: 8D) the status register via the I2C bus, and then select the sync priority depending on this status. Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and (when 12 V is supplied) whether a Vext has been extracted from H/HVIN. Both horizontal and vertical sync are detected even if only 5 V is supplied. In order to choose the right sync priority the MCU may proceed as follows (see I 2C Address Table): Of course, when the choice is made, we can refresh the sync detections and verify that the extracted Vsync is present and that no sync type change has occurred. The sync processor also gives sync polarity information. 1.7 IC status The IC can inform the MCU about the 1st horizontal PLL and vertical section status (locked or not) and about the XRAY protection (activated or not).Resetting the XRAY internal latch can be done either by decreasing the VCC supply or directly resetting it via the I2C interface. 1.8 Sync Inputs Both H/HVIN and VSYNCIN inputs are TTL compatible triggers with hysteresis to avoid erratic detection. Both inputs include a pull up resistor connected to VDD. * * * refresh the status register wait at least for 20ms (Max. vertical period) read this status register Sync priority choice should be: Sync priority Subaddress 03 (D8) 1 0 Vextd et No Yes HV det Yes Yes V det Yes No Comment Sync type Separated H&V Composite TTL H&V 1.9 Sync Processor Output The sync processor indicates on the D8 bit of the status register whether 1st PLL is locked to an incoming horizontal sync. Its level goes to low when locked. This information is also available on pin 3 when sub-address 02 D8 is equal to 1. When PLL1 is unlocked, pin 3 output voltage goes to 5V. 2 HORIZONTAL PART 2.1 Internal Input Conditions A digital signal (horizontal sync pulse or TTL composite) is sent by the sync processor to the horizontal input. It may be positive or negative (see Figure 5). Using internal integration, both signals are recognized if Z/T < 25%. Synchronization occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7 s. Another integration is able to extract the vertical pulse from composite sync if the duty cycle is higher than 25% (typically d = 35%), (see Figure 6). 28/47 TDA9109A Figure 5. Figure 6. The last feature performed is the removal of equalization pulses to avoid parasitic pulses on the phase comparator (which would be disturbed by missing or extraneous pulses). This last feature is switched on/off by sub-address 0F D8. By default [0], equalization pulses will not be removed. 2.2 PLL1 The PLL1 consists of a phase comparator, an external filter and a voltage-controlled oscillator (VCO).The phase comparator is a "phase frequency" type designed in CMOS technology. This kind Figure 7. of phase detector avoids locking on wrong frequencies. It is followed by a "charge pump", composed of two current sources : sunk and sourced (typically I =1 mA when locked and I = 140 A when unlocked). This difference between lock/unlock allows smooth catching of the horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system when PLL1 is locked, avoiding the horizontal frequency changing too quickly. The dynamic behavior of PLL1 is fixed by an external filter which integrates the current of the charge pump. A "CRC" filter is generally used (see Figure 7) PLL1F 7 1.8k 10nF 4.7F 29/47 TDA9109A The PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong pulses on phase Figure 8. comparator. Inhibition is obtained by stopping high and low signals at the entry of the charge pump block (see Figure 8). Figure 9. The VCO uses an external RC network. It delivers a linear sawtooth obtained by the charge and the discharge of the capacitor, with a current proportional to the current in the resistor. The typical thresholds of the sawtooth are 1.6 V and 6.4 V. The control voltage of the VCO is between 1.4 V and 6.4 V (see Figure 9). The theoretical frequency range of this VCO is in the ratio of 1 to 4.5. The effective frequency range has to be smaller (1 to 4.2) due to clamp intervention on the filter lowest value. The sync frequency must always be higher than the free running frequency. For example, when using a sync range between 24.8 kHz and 100 kHz, the suggested free running frequency is 23 kHz. PLL1 ensures the coincidence between the leading edge of the sync signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage which is I2C adjustable between 2.9 V and 4.2 V (corresponding to 10 %) (see Figure 10). 30/47 TDA9109A The TDA9109A also includes a Lock/Unlock identification block which senses in real time whether PLL1 is locked or not on the incoming horizontal sync signal. The lock/unlock information is available through the I2C read and the pin 3 voltage level PLL1 Timing Diagram Figure 10. H O SC Sawtooth 7/8 TH 1/8 TH Figure 11. PLL2 Timing Diagram HOsc Sawtooth 7/8TH 1/8 TH 6.4V 4.0V 1.6V 6.4V Ref. for H Position Vb (2.9V 2.3 PLL2 PLL2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the VCO, taking into account the saturation time Ts (see Figure 11) The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output current: 0.5 mA). The flyback input consists of an NPN transistor. This input must be current driven. The maximum recommended input current is 5 mA (see Figure 12). Figure 12. Flyback Input Electrical Diagram 500 HFly 12 20k Q1 GND 0V The duty cycle is adjustable through I2C from 30 % to 65 %. For a safe start-up operation, the initial duty cycle (after power-on reset) is 65% in order to avoid having too long a conduction period of the horizontal scanning transistor. The maximum storage time (Ts Max.) is (0.44THTFLY/2). Typically, TFLY/TH is around 20 % which means that Ts max is around 34 % of TH. 31/47 TDA9109A 2.4 Output Section The H-drive signal is sent to the output through a shaping stage which also controls the H-drive duty cycle (I2C adjustable) (see Figure 11). In order to secure the scanning power part operation, the output is inhibited in the following cases: * * * * when VCC or VDD are too low when the XRAY protection is activated during the Horizontal flyback when the HDrive I2C bit control is off This output stage is intended for "reverse" base control, where setting the output NPN in off-state will control the power scanning transistor in offstate. The maximum output current is 30mA, and the corresponding voltage drop of the output VCEsat is 0.4V Max. Obviously the power scanning transistor cannot be directly driven by the integrated circuit. An interface has to be added between the circuit and the power transistor either of bipolar or MOS type. 2.5 X-RAY Protection The X-Ray protection is activated by application of a high level on the X-Ray input (8.2V on Pin 25). It inhibits the H-Drive and B+ outputs. This activation is internally delayed by 2 lines to avoid erratic detection (short parasitics). This protection is latched; it may be reset either by VCC switch off or by I2C (see Figure 14). The output stage consists of a NPN bipolar transistor. Only the collector is accessible (see Figure 13). Figure 13. Figure 14. Safety Functions Block Diagram 32/47 TDA9109A 2.6 Horizontal and Vertical Dynamic Focus The TDA9109A delivers a horizontal parabola which is added on a vertical parabola waveform on Pin 10. This horizontal parabola comes from a sawtooth in phase advance with flyback pulse middle. The time advance versus horizontal flyback middle is kept constant versus frequency (about 1s). Symmetry and amplitude are I2C adjustable (see Figure 15). The vertical dynamic focus is tracked with VPOS and VAMP. Its amplitude can be adjusted. It is also affected by S and C corrections. This positive signal once amplified is to be sent to the CRT focusing grids. Figure 15. Phase of HFocus Parabola 33/47 TDA9109A 3 VERTICAL PART 3.1 Function When the synchronization pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 100Hz. The typical free running frequency can be calculated by: 1 fo(Hz) = 1.5 . 10-5 . 3.2 I2C Control Adjustments S and C correction shapes can then be added to this ramp. These frequency-independent S and C corrections are generated internally. Their amplitudes are adjustable by their respective I2C registers. They can also be inhibited by their "select" bits. Finally, the amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude control register. The adjusted ramp is available on Pin 23 (VOUT) to drive an external power stage. The gain of this stage can be adjusted ( 25%) depending on its register value. The mean value of this ramp is driven by its own I2C register (vertical position). Its value is VPOS = 7/16 . VREF-V 400mV. Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from VREF-V, the bias voltage sent to the noninverting input of the booster should also derive from VREF-V to optimize the accuracy (see Application Diagram). 3.3 Vertical Moire By using the vertical moire, VPOS can be modulated from frame to frame. This function is intended to cancel the fringes which appear when the line to line interval is very close to the CRT vertical pitch. The amplitude of the modulation is controlled by register VMOIRE on sub-address 0C and can be switched-off via the control bit D8. COSC A negative or positive TTL level pulse applied on Pin 2 (VSYNC) as well as a TTL composite sync on Pin 1 can synchronize the ramp in the range [fmin, fmax] (See Figure 16). This frequency range depends on the external capacitor connected on Pin 22. A 150nF ( 5%) capacitor is recommended for 50Hz to 185Hz applications. If a synchronization pulse is applied, the internal oscillator is synchronized immediately but with wrong amplitude. An internal correction then adjusts it in less than half a second. The top value of the ramp (Pin 22) is sampled on the AGC capacitor (Pin 20) at each clock pulse and a transconductance amplifier modifies the charge current of the capacitor in such a way to make the amplitude constant again. The read status register provides the vertical LockUnlock and the vertical sync polarity information. We recommend the use of an AGC capacitor with low leakage current. A value lower than 100nA is mandatory. A good stability of the internal closed loop is reached by a 470nF 5% capacitor value on Pin 20 (VAGC). 34/47 TDA9109A Figure 16. AGC Loop Block Diagram Charge Current Transconductance Amplifier REF 22 Discharge. VSYNCIN 2 Synchro Polarity Oscillator OSC CAP Sampling Sampling Capacitance S Correction VS Amp sub-add 07/7bits Cor_C sub-add 08/7bits C Correction Vlow 18 BREATH sawth. disch. 23 VOut Vert. Amp VMoire sub.0C/7bits sub.06/7bits sub-.05/7bits V Position 3.4 Basic Equations In first approximation, the amplitude of the ramp on Pin 23 (VOUT) is: VOUT - VPOS = (VOSC - VDCMID) . (1 + 0.3 (VAMP )) where: VDCMID = 7/16 VREF (middle value of the ramp on Pin 22, typically 3.6V) VOSC = V22 (ramp with fixed amplitude) VAMP = -1 for minimum vertical amplitude register value and +1 for maximum VPOS is calculated by: VPOS = VDCMID + 0.4 VP where VP = -1 for minimum vertical position register value and +1 for maximum. The current available on Pin 22 is: 3. IOSC = VREF . C OSC . f 8 where COSC = capacitor connected on Pin 22 and f = synchronization frequency. Geometric Corrections The principle is represented in Figure 17. Starting from the vertical ramp, a parabola-shaped current is generated for E/W correction (also known as Pin Cushion correction), dynamic horizontal phase control correction, and vertical dynamic focus correction. The parabola generator is made by an analog multiplier, the output current of which is equal to: I = k . (VOUT - VDCMID)2 where VOUT is the vertical output ramp (typically between 2 and 5V) and VDCMID is 3.6V (for VREF-V = 8.2V). The VOUT sawtooth is typically centered on 3.6V. By changing the vertical position, the sawtooth shifts by 0.4V. To provide good screen geometry for any end user adjustment, the TDA9109A has the "geometry tracking" feature which allows generation of a dissymetric parabola depending on the vertical position. Due to the large output stage voltage range (E/W Pin Cushion, Keystone, E/W Corner), the combination of the tracking function, maximum vertical amplitude, maximum or minimum vertical position and maximum gain on the DAC control may lead to output stage saturation. This must be avoided by limiting the output voltage with appropriate I2C register values. 35/47 TDA9109A For the E/W part and the dynamic horizontal phase control part, a sawtooth-shaped differential current in the following form is generated: I' = k' . (VOUT - VDCMID) Then I and I' are added and converted into voltage for the E/W part. Each of the two E/W components or the two dynamic horizontal phase control components may be inhibited by their own I2C select bit. The E/W parabola is available on Pin 24 via an emitter follower output stage which has to be biased by an external resistor (10k to ground). Since stable in temperature, the device can be DC coupled with external circuitry. The vertical dynamic focus is combined with the horizontal focus on Pin 10. The dynamic horizontal phase control drives internally the H-position, moving the HFLY position on the horizontal sawtooth in the range of 2.8 %TH both for side pin balance and parallelogram. Figure 17. Geometric Corrections Principle 3.5 E/W EWOUT = EWDC + K1 (VOUT - VDCMID) + K2 (VOUT - VDCMID)2+ K3 (VOUT - VDCMID)4 K1 is adjustable by the keystone I2C register. K2 is adjustable by the E/W amplitude I2C register. K3 is adjustable by the E/W corner I2C register. 3.6 Dynamic Horizontal Phase Control IOUT= K4 (VOUT - VDCMID) + K5 (VOUT - VDCMID)2 K4 is adjustable by the parallelogram I2C register. K5 is adjustable by the side pin balance I2C register. 36/47 TDA9109A 4 DC/DC CONVERTER PART This unit controls the switch-mode DC/DC converter. It converts a DC constant voltage into the B+ voltage (roughly proportional to the horizontal frequency) necessary for the horizontal scanning. This DC/DC converter can be configured either in step-up or step-down mode. In both cases it operates very similarly to the well known UC3842. 4.1 Step-up Mode Operating Description 4.2 Step-down Mode In step-down mode, the ISENSE information is not used any more and therefore not sent to the Pin16. This mode is selected by connecting Pin16 to a DC voltage higher than 6V (for example VREFV). Operating Description * * * The power MOS is switched-on as for the step-up mode The feedback to the error amplifier is done as for the step-up mode * * The power MOS is switched-on during the flyback (at the beginning of the positive slope of the horizontal focus sawtooth). The power MOS is switched-off when its current reaches a predetermined value. For this purpose, a sense resistor is inserted in its source. The voltage on this resistor is sent to Pin16 (ISENSE). The feedback (coming either from the EHV or from the flyback) is divided to a voltage close to 5.0V and compared to the internal 5.0V reference (IVREF). The difference is amplified by an error amplifier, the output of which controls the power MOS switch-off current. The power MOS is switched-off when the HFOCUSCAP voltage get higher than the error amplifier output voltage Main Features * * * * Switching synchronized on the horizontal frequency B+ voltage always lower than the DC source No current limitation 4.3 Step-up and Step-down Mode Comparison In step-down mode the control signal is inverted compared with the step-up mode. The reason for this, is the following: Main Features * * * * * * Switching synchronized on the horizontal frequency B+ voltage always higher than the DC source Current limited on a pulse-by-pulse basis when VCC or VDD are too low when X-Ray protection is latched directly through I2C bus * * In step-up mode, the switch is a N-channel MOS referenced to ground and made conductive by a high level on its gate. In step-down, a high-side switch is necessary. It can be either a P- or a N-channel MOS. - For a P-channel MOS, the gate is controlled directly from Pin 28 through a capacitor (this allows to spare a Transformer). In this case, a negative-going pulse is needed to make the MOS conductive. Therefore it is necessary to invert the control signal. - For a N-channel MOS, a transformer is needed to control the gate. The polarity of the transformer can be easily adapted to the negative-going control pulse. The DC/DC converter is disabled: When disabled, BOUT is driven to GND by a 0.5mA current source. This feature allows to implement externally a soft start circuit. 37/47 TDA9109A Figure 18. DC/DC Convertor I2 C DAC 7bits Horizontal Dynamic Focus Sawtooth + C1 1/3 1.3V 1.3V C3 6V C4 C2 HDF Disc 400ns BOUT 12V Iadjust 6.2V 5V20% 85dB A inhibit Soft start down down up S R Q 28 up inhibit Command step-up/down 8V REGIN 15 22k 14 COMP ISENSE 16 TDA9109A 1M L EHV Feedback VB+ 38/47 TDA9109A INTERNAL SCHEMATICS Figure 19. Figure 22. Figure 20. Figure 23. HREF 13 12V R0 6 Figure 21. Figure 24. 39/47 TDA9109A Figure 25. Figure 28. Figure 26. Figure 29. Figure 27. Figure 30. 40/47 TDA9109A Figure 31. Figure 34. Figure 32. Figure 35. Figure 33. Figure 36. 41/47 TDA9109A Figure 37. Figure 38. Figure 39. 42/47 TDA9109A Figure 40. Demonstration Board J16 J15 1 J14 2 34 C39 22 pF R29 R 42 4.7k 1 00 R41 100 +12 V CC2 10F CC 3 47p F CC1 100nF TP13 PC1 47k TP17 J12 -12V 9 J11 TP1 IC4 TDA9109A 1 H/HVIN +5V +5V L1 22H R39 4.7k C32 100nF TP16 2 VSYNCIN TP10 +5V 32 C30 100F SDA 31 C40 22pF SCL SDA 13 14 1 5 16 17 18 19 20 21 22 23 24 PWM4 PWM5 SCL SDA XTALOUT RST GND R G B TEST PWM6 PWM7 C45 10F IC3-STV9422 R49 22k +5V 1 6 15 14 13 12 11 10 VCC 1 TA1 TB1 TA2 2 IA CDB TB2 CDA 3 4 IB IA 5 IB QA 6 QB QA 7 R90 10k () R78 10 3 HLock o ut C7 22nF 4 PL L2C C28 820pF 5% 5 C0 SCL 30 ICC1 MC1 4528 8 QB GND HSYNC V DD XTALIN CKOUT VSYNC PWM3 PWM2 PWM1 PWM0 PXCK FBLK VCC 29 C6 100nF B+OUT 28 C5 100F +12V 12 11 10 X1 9 8 7 6 5 4 3 2 1 R43 10k CC4 47pF PC2 47k TILT J13 +12 V R10 1 0k C 25 3 3pF R23 (***) 6 R0 C13 10 nF 7 PL L1F HOUT 26 R 36 1.8k C31 4.7F 8H XRAY 25 C17 47 0nF POSITION TP14 9 HFOCUSEWOUT 24 CAP VOUT 23 GND 27 +12V R53 1k HOUT C49 10 0nF R56 560k C4 8 10F D2 1N4148 8MHz C38 33pF C37 33pF C 43 +5V R30 47F 10k C42 1F C36 1F R35 +12V 10k HOUT J8 C22 33p F R8 10k +12V R7 10k R45 33k R37 27k R34 1k R15 1k R17 43k (* *) HFLY J9 DYN FOCUS R25 1k R24 10k L 47H C34 820pF 5% Q1 Q2 BC557 BC557 E/W POWER STAGE TP22 R 31 27 k (**) R38 R19 2.2 J1 270k 3W C11220 pF R18 10k (**) Q3 TIP122 E/W 10 FOCUS OUT 11 HGND +12V C12 VCAP 22 150nF R5 2 3.9k R9 470 R33 4.7k J19 1 2 3 4 CON4 C16 (*) C27 47F C 33 HREF 1 00nF 12 HFLY VR EF 21 C15 C3 47F R2 5 .6k R40 36k 13 HREF VAGCCAP 20 JP1 R50 1M R89 33k C51 22F C46 1nF C2 470nF 100nF C4 100nF C14 470F D1 1n40 04 C1 0 100F 35V C9 100nF TP6 +12V -1 2V TP4 TP3 J2 J3 TP7 C1 R3 220nF 1.5 14 COMP VGND 19 IC1 TDA81 72 C10 -12V 470F J6 1 R11 VYOKE 2 220 0.5W 3 R4 1 0.5W J18 RE GIN R51 1k D10 1N4148 15 REGIN BR EATH 18 R1 12k ISENSE GND C47 100pF 16 ISENSE B+GND 17 C 41 470pF C8 100nF R5 5.6 R58 10 B+OUT +12V R73 R75 1M 10k R76 47k P1 10k R74 10k R77 15k D9 1N4148 D8 1N4148 Q4 BC5 57 VER TICA L D EFLECTION STAGE J17 HOUT L3 22H +12V Q5 BC547 C50 10F TP8 EHT COMP C 60 1 00nF (*) op tional (**) see table 9109A R7 8 R9 0 R3 1 R1 7 R1 8 Shorted Removed Mou nted 270k 39k 9111 Mount ed Mount ed Re moved 43k 10k (***) For R23=6.49k f 0=22.8 kHz typ For R 23=5.23k f 0=28.3 kHz typ 43/47 TDA9109A Figure 41. PCB Layout 44/47 TDA9109A Figure 42. Components Layout 45/47 TDA9109A PACKAGE MECHANICAL DATA 32 PINS - PLASTIC SHRINK E E1 A2 A1 A C L B B1 e Stand-off eA eB D 32 17 1 16 Millimeters Min. 3.556 0.508 3.048 0.356 0.762 .203 27.43 9.906 7.620 3.556 0.457 1.016 0.254 27.94 10.41 8.890 1.778 10.16 12.70 2.540 3.048 3.810 0.100 0.120 4.572 0.584 1.397 0.356 28.45 11.05 9.398 Typ. 3.759 Max. 5.080 Min. 0.140 0.020 0.120 0.014 0.030 0.008 1.080 0.390 0.300 0.140 0.018 0.040 0.010 1.100 0.410 0.350 0.070 0.400 0.500 0.150 0.180 0.023 0.055 0.014 1.120 0.435 0.370 Dimensions A A1 A2 B B1 C D E E1 e eA eB L Inches Typ. 0.148 Max. 0.200 46/47 TDA9109A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philip s. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www .st.com 47/47 |
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